1. Field of the Invention
The present invention relates to a signal receiving circuit and a method for receiving signals, and more particularly to the signal receiving circuit and the method for receiving signals used by a receiving terminal carrying out communications with a transmitting terminal in an asynchronous manner.
The present application claims priority of Japanese Patent Application No. 2000-059265 filed on Mar. 3, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
Digital communications for transmitting and receiving digital signals are widely used. In some cases, communications are carried out between terminals via asynchronous transmission, without the use of synchronous signals. Even in the case of asynchronous digital communications, it is desired that a receiving terminal receives signals at the same sampling frequency that a transmitting terminal uses to transmit signals. To achieve this, each of the transmitting and receiving terminals has a clock signal generating circuit adapted to generate a clock signal at the same sampling frequency.
However, it is actually impossible for each of the transmitting and receiving terminals to generate a clock signal at the exact same frequency, and to transmit and receive signals at the exact same sampling frequency. For example, when signals are transmitted and received at a sampling frequency of 16 kHz, a frequency difference of about 40 Hz occurs. This means that the number of pieces of sample data contained in a transmitting signal, which is generated by the transmitting terminal, differs by 4 pieces per one second from the number of pieces of sample data that the receiving terminal is prepared to receive.
When the number of pieces of the sample data contained in the transmitting signal, which is generated by the transmitting terminal, is different from the number of pieces of the sample data to be received by the receiving terminal, the receiving terminal uses a signal receiving circuit adapted to solve the problem of the difference in the number of pieces of data.
Such a signal receiving circuit is disclosed in Japanese Patent Application Laid-open No. Hei 8-32562, as shown in FIG. 7. A conventionally known signal receiving circuit 200 is used to receive a digital voice signal. As shown in FIG. 7, the signal receiving circuit 200 is provided with a digital voice input terminal 101. The digital voice input terminal 101 is connected to a buffer memory 102. Moreover, the signal receiving circuit 200 has a writing clock input terminal 103.
The writing clock input terminal 103 is connected to a writing address counter 104. The writing address counter 104 is connected to the buffer memory 102 and to a slip monitoring circuit 105. The signal receiving circuit 200 further has a reading clock input terminal 106. The reading clock input terminal 106 is connected to a reading address counter 107. The reading address counter 107 is connected to the buffer memory 102 and to the slip monitoring circuit 105. The buffer memory 102 is connected to a sound level calibrating circuit 108. The slip monitoring circuit 105 is connected to the sound level calibrating circuit 108. The sound level calibrating circuit 108 is connected to a digital voice output terminal 109.
Operations of the conventional signal receiving circuit 200 will be described. A digital voice input signal A, input from the digital voice input terminal 101, is written into the buffer memory 102 sequentially. A writing clock signal B is input from the writing clock input terminal 103. The writing clock signal B is in sync with the digital voice input signal A. A writing address C is output from the writing address counter 104. A signal carrying the writing address C is in sync with the writing clock signal B. The writing address C is fed to the buffer memory 102. The digital voice input signal A is written to an address designated by the writing address C and stored in the buffer memory 102.
A reading clock signal D is fed to the reading address counter 107 from the reading clock input terminal 106. A reading address E is output from the reading address counter 107. A signal carrying the reading address E is in sync with the reading clock signal D. The reading address E is fed to the buffer memory 102. The buffer memory 102 outputs the signal stored in the address designated by the reading address E as an output digital voice signal F to the sound level calibrating circuit 108.
The writing address C and the reading address E are input to the slip monitoring circuit 105. The slip monitoring circuit 105 monitors the writing address C and the reading address E at all times. The slip monitoring circuit 105 outputs a sound level control starting signal G to the sound level calibrating circuit 108 when the differential between the writing address C and reading address E approaches a predetermined value. The sound level 90 calibrating circuit 108 outputs the output digital voice signal F. When the sound level calibrating circuit 108 receives the sound level control starting signal G, decay begins to occur in the amplitude of an output digital voice signal F′. The sound level calibrating circuit 108 minimizes the amplitude of the output 95 digital voice signal F′ ten seconds after the sound level control starting signal G has been input.
The slip monitoring circuit 105, “t1” seconds after the amplitude of the output digital voice signal F′ has been minimized, that is, “t0+t1” seconds after the sound level control starting signal G has been input to the sound level calibrating circuit 108, outputs a reading address switching signal H to the reading address counter 107. The reading address E is switched in response to the reading address switching signal H. “t1” seconds after the reading address E has been switched, the amplitude of the output 105 digital voice signal F′ gradually increases and the output digital voice signal F′ is restored to its original level.
In the signal receiving circuit 200, if the writing clock signal B is not in sync with the signal of the reading address E, a dropout and/or overlap of data occurs. When the dropout and/or 110 overlap of data occurs, the reading address E is switched. Before the reading address E is switched, the output digital voice signal F′ is gradually decreased in sound level.
After the reading address E has been switched, the sound level of the output digital voice signal F′ is gradually restored to its original level. When the reading address E has been switched, voice noise that has occurred due to the dropout and/or overlap of data is removed. In the conventional signal receiving circuit 200, no further discontinuity in a signal waveform of the output digital voice signal F′ occurs.
In the conventional signal receiving circuit 200, if the dropout and/or overlap of data occurs, the amplitude of the output digital voice signal F′ is minimized for “t1” seconds. During the “t1” seconds after the dropout and/or overlap has occurred, there is essentially no output in the output digital voice signal F′. For example, when the output digital voice signal F′ is output via a speaker, there is a time when no sound is produced. The output digital voice signal F′ is discontinuous on a time axis.
It is desired that no discontinuity in the signal waveform contained in sample data to be received by the receiving terminal on the time axis should occur even when the number of pieces of sample data to be transmitted by the transmitting terminal does not coincide with that of sample data to be received by the receiving terminal.